{"id":14429,"date":"2022-04-29T11:07:30","date_gmt":"2022-04-29T17:07:30","guid":{"rendered":"https:\/\/www.vicmyers.com\/?p=14429"},"modified":"2022-04-29T12:09:54","modified_gmt":"2022-04-29T18:09:54","slug":"deploying-xilinx-zynq-ultrascale-rfsoc","status":"publish","type":"post","link":"https:\/\/www.vicmyers.com\/deploying-xilinx-zynq-ultrascale-rfsoc\/","title":{"rendered":"Deploying Xilinx Zynq UltraScale+ RFSoC"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"14429\" class=\"elementor elementor-14429\" data-elementor-post-type=\"post\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-6bc452a elementor-section-stretched elementor-section-full_width elementor-section-height-default elementor-section-height-default\" data-id=\"6bc452a\" data-element_type=\"section\" data-settings=\"{&quot;stretch_section&quot;:&quot;section-stretched&quot;}\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-6279f1f\" data-id=\"6279f1f\" data-element_type=\"column\" data-settings=\"{&quot;background_background&quot;:&quot;classic&quot;}\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-8527df1 elementor-widget elementor-widget-theme-post-featured-image elementor-widget-image\" data-id=\"8527df1\" data-element_type=\"widget\" data-widget_type=\"theme-post-featured-image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.21.0 - 15-04-2024 *\/\n.elementor-widget-image{text-align:center}.elementor-widget-image a{display:inline-block}.elementor-widget-image a img[src$=\".svg\"]{width:48px}.elementor-widget-image img{vertical-align:middle;display:inline-block}<\/style>\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"500\" height=\"266\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2018\/12\/whitepaper.jpg\" class=\"attachment-full size-full wp-image-1103\" alt=\"product resource whitepaper\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2018\/12\/whitepaper.jpg 500w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2018\/12\/whitepaper-300x160.jpg 300w\" sizes=\"(max-width: 500px) 100vw, 500px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f75c462 elementor-widget elementor-widget-theme-post-title elementor-page-title elementor-widget-heading\" data-id=\"f75c462\" data-element_type=\"widget\" data-widget_type=\"theme-post-title.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.21.0 - 15-04-2024 *\/\n.elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px}<\/style><h1 class=\"elementor-heading-title elementor-size-default\">Deploying Xilinx Zynq UltraScale+ RFSoC<\/h1>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ce1d457 elementor-widget elementor-widget-spacer\" data-id=\"ce1d457\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.21.0 - 15-04-2024 *\/\n.elementor-column .elementor-spacer-inner{height:var(--spacer-size)}.e-con{--container-widget-width:100%}.e-con-inner>.elementor-widget-spacer,.e-con>.elementor-widget-spacer{width:var(--container-widget-width,var(--spacer-size));--align-self:var(--container-widget-align-self,initial);--flex-shrink:0}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container,.e-con>.elementor-widget-spacer>.elementor-widget-container{height:100%;width:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer{height:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner{height:var(--container-widget-height,var(--spacer-size))}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty,.e-con>.elementor-widget-spacer.elementor-widget-empty{position:relative;min-height:22px;min-width:22px}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon,.e-con>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon{position:absolute;top:0;bottom:0;left:0;right:0;margin:auto;padding:0;width:22px;height:22px}<\/style>\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f6d3fb9 elementor-widget elementor-widget-text-editor\" data-id=\"f6d3fb9\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.21.0 - 15-04-2024 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#69727d;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#69727d;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<span style=\"color: #d10202; font-size: 20px;\">\n On February 21st, 2017, Xilinx\u00ae announced the introduction of a new\ntechnology called RFSoC. The proposition was simple;\nadd RF-class analog to digital and digital to analog data converters\nto Xilinx\u2019s already powerful MPSoC, ARM processor enhanced family\nof high performance FPGAs. And while the concept was simple, the\nimplications were profound.<\/span>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f481339 elementor-share-buttons--view-icon elementor-share-buttons--shape-rounded elementor-share-buttons--align-left elementor-share-buttons--skin-gradient elementor-grid-0 elementor-share-buttons--color-official elementor-widget elementor-widget-global elementor-global-4304 elementor-widget-share-buttons\" data-id=\"f481339\" data-element_type=\"widget\" data-widget_type=\"share-buttons.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<link rel=\"stylesheet\" href=\"https:\/\/www.vicmyers.com\/wp-content\/plugins\/elementor-pro\/assets\/css\/widget-share-buttons.min.css\">\t\t<div class=\"elementor-grid\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_linkedin\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on linkedin\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fab-linkedin\" viewBox=\"0 0 448 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M416 32H31.9C14.3 32 0 46.5 0 64.3v383.4C0 465.5 14.3 480 31.9 480H416c17.6 0 32-14.5 32-32.3V64.3c0-17.8-14.4-32.3-32-32.3zM135.4 416H69V202.2h66.5V416zm-33.2-243c-21.3 0-38.5-17.3-38.5-38.5S80.9 96 102.2 96c21.2 0 38.5 17.3 38.5 38.5 0 21.3-17.2 38.5-38.5 38.5zm282.1 243h-66.4V312c0-24.8-.5-56.7-34.5-56.7-34.6 0-39.9 27-39.9 54.9V416h-66.4V202.2h63.7v29.2h.9c8.9-16.8 30.6-34.5 62.9-34.5 67.2 0 79.7 44.3 79.7 101.9V416z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_facebook\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on facebook\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fab-facebook\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M504 256C504 119 393 8 256 8S8 119 8 256c0 123.78 90.69 226.38 209.25 245V327.69h-63V256h63v-54.64c0-62.15 37-96.48 93.67-96.48 27.14 0 55.52 4.84 55.52 4.84v61h-31.28c-30.8 0-40.41 19.12-40.41 38.73V256h68.78l-11 71.69h-57.78V501C413.31 482.38 504 379.78 504 256z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_email\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on email\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fas-envelope\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M502.3 190.8c3.9-3.1 9.7-.2 9.7 4.7V400c0 26.5-21.5 48-48 48H48c-26.5 0-48-21.5-48-48V195.6c0-5 5.7-7.8 9.7-4.7 22.4 17.4 52.1 39.5 154.1 113.6 21.1 15.4 56.7 47.8 92.2 47.6 35.7.3 72-32.8 92.3-47.6 102-74.1 131.6-96.3 154-113.7zM256 320c23.2.4 56.6-29.2 73.4-41.4 132.7-96.3 142.8-104.7 173.4-128.7 5.8-4.5 9.2-11.5 9.2-18.9v-19c0-26.5-21.5-48-48-48H48C21.5 64 0 85.5 0 112v19c0 7.4 3.4 14.3 9.2 18.9 30.6 23.9 40.7 32.4 173.4 128.7 16.8 12.2 50.2 41.8 73.4 41.4z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_print\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on print\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fas-print\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M448 192V77.25c0-8.49-3.37-16.62-9.37-22.63L393.37 9.37c-6-6-14.14-9.37-22.63-9.37H96C78.33 0 64 14.33 64 32v160c-35.35 0-64 28.65-64 64v112c0 8.84 7.16 16 16 16h48v96c0 17.67 14.33 32 32 32h320c17.67 0 32-14.33 32-32v-96h48c8.84 0 16-7.16 16-16V256c0-35.35-28.65-64-64-64zm-64 256H128v-96h256v96zm0-224H128V64h192v48c0 8.84 7.16 16 16 16h48v96zm48 72c-13.25 0-24-10.75-24-24 0-13.26 10.75-24 24-24s24 10.74 24 24c0 13.25-10.75 24-24 24z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-755adee elementor-widget elementor-widget-text-editor\" data-id=\"755adee\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">Xilinx Zynq ULtraScale+ RFSoC is changing the way engineers can design and package small, high channel count systems. This technology not only offers new possibilities for 5G applications, but has significant impact in military and scientific systems, justifying the claim in Xilinx\u2019s announcement that \n\u201cXilinx Unveils Disruptive Integration and Architectural Breakthrough for 5G Wireless with RF-Class Analog Technology.\u201d \n<\/p>\n<p class=\"p1\">\nTo get better appreciation of the capabilities of RFSoC and understand how to best use the advantages of this technology, it\u2019s worth taking a quick look at current trends in data converters and signal processing. <\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-4592b50 elementor-widget elementor-widget-text-editor\" data-id=\"4592b50\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h2 style=\"color: #d10202; font-size: 23px;\">What is RFSoC?<\/h2>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-22e1496 elementor-widget elementor-widget-text-editor\" data-id=\"22e1496\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">RFSoC or more properly, Zynq\u00ae UltraScale+\u2122 RFSoC is based on Xilinx\u2019s prior family, the Zynq\nUltraScale+ MPSoC. The MPSoC is a system on chip architecture that includes up to four ARM\nCortex-A53 application processors and two ARM Cortex-R5 real-time processors integrated into the\nUltraScale+ programmable logic. This solution offers the software programmability and flexibility of\na processor with the hardware programmability and performance of an FPGA in a single IC.<\/p>\n<p class=\"p1\">\nRFSoC builds on the MPSoC foundation and adds eight 5 GSPS 14-bit A\/Ds each equipped with\nprogrammable Digital Downconverts (DDC) and eight 10 GSPS 14-bit D\/As each equipped with Digital\nUpconverters (DUC). While other A\/D and D\/A configurations are available, we\u2019ll consider the eight\nA\/D and eight D\/A configuration for the rest of this paper. Below is an image that shows the similarity\nbetween the MPSoC and RFSoC.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-dbcd868 elementor-widget elementor-widget-image\" data-id=\"dbcd868\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"600\" height=\"268\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-zynq-ultascale.jpg\" class=\"attachment-large size-large wp-image-14432\" alt=\"xilinx zynq ultrascale\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-zynq-ultascale.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-zynq-ultascale-300x134.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 1 - Xilinx's Zynq UltraScale MPSoC vs. RFSoC<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-665c3e6 elementor-widget elementor-widget-text-editor\" data-id=\"665c3e6\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h2 style=\"color: #d10202; font-size: 23px;\">Improvements in SWaP and Cost<\/h2>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-7f05d06 elementor-widget elementor-widget-text-editor\" data-id=\"7f05d06\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">A common term in military applications is SWaP, which stands for Size, Weight and Power and refers\nto the ongoing requirement to reduce these attributes for communications, reconnaissance, radar\nand various types of signal acquisition and processing systems. The need for smaller, lighter and less\npower becomes obvious when you think about where these systems are often deployed. Unmanned\nvehicles like unmanned aerial vehicles (UAV) and unmanned underwater vehicles (UUV) frequently\nrequire stealth to achieve their mission. Smaller, lighter and less power usually equates to stealthier,\nenabling these systems to be more effective.<\/p>\n<p class=\"p1\">\nManpack (or womanpack) systems where the communications or direction finding equipment and\nassociated power supply are worn by personnel are another target for SWaP reduction. Here again,\nsmaller, lighter and less power is needed for making a practical, human carried system.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d52a26a elementor-widget elementor-widget-image\" data-id=\"d52a26a\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"600\" height=\"244\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component.jpg\" class=\"attachment-large size-large wp-image-14433\" alt=\"Discrete component vs. RFSoC solution size comparison\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component-300x122.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 2 \u2013 Discrete component vs. RFSoC solution size comparison<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d2689e2 elementor-widget elementor-widget-spacer\" data-id=\"d2689e2\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-321620c elementor-widget elementor-widget-text-editor\" data-id=\"321620c\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">RFSoC\u2019s high level of integration provides a significant amount of SWaP reduction when compared to\ndesigning the same functionality with discrete components. The example below shows the reduction\nin size by representing component footprints graphically. In the comparison, each component is\nroughly to scale, and space has been left between the discrete components to model a typical PCB\nlayout, where ICs need space between them for assembly and placement of passive components.\nThe RFSoC implementation can save 50% or more in overall size compared to the discrete approach.\n<\/p>\n<p class=\"p1\">\nWhile RFSoC can reduce weight at the component level, that savings is minimal when you consider the\ntotal weight of nine ICs compared to a single RFSoC. Where weight savings can be appreciated is when\nyou look at power. For every watt of power in a system, comes the weight of a cooling solution, either in metal or composite heatsinks, or in some systems, more exotic solutions like liquid and vapor\ncooling. RFSoC can easily bring power savings of 30%-40% or more compared to typical discrete\nsolutions reducing the cooling solution complexity and weight. And in portable systems, every watt\nthat can be eliminated results in smaller, lighter batteries and longer operation time.<\/p>\n<p class=\"p1\">\nA key reason for the reduced power of RFSoC is the elimination of the interfaces needed to connect the\nvarious ICs in a discrete solution. Most data converters sampling at 1 or 2 GHz or higher depend on\nserial interfaces to move digital data between the converter and the FPGA. These interfaces expend\npower at both the data converter side and the FPGA side in serializing and deserializing (SerDes)\ncircuitry. The most common serial interface protocol used for converters is JESD204. By integrating\nthe converters directly into the FPGA, the serial interfaces are eliminated as well as data transfer\nlatency which the SerDes process and protocol introduce. (More on serial vs. parallel converter\ninterfaces and latency later in this paper)\n<\/p>\n<p class=\"p1\">\nAnother parameter often tacked on to SWaP is cost, sometimes referred to as SWaP-C. Here again\nRFSoC address the requirement. The same comparison used earlier of implementing the functions of\nthe RFSoC as discrete components yields the following results:<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-c4efc1a elementor-widget elementor-widget-image\" data-id=\"c4efc1a\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"202\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component-cost-compare.jpg\" class=\"attachment-large size-large wp-image-14434\" alt=\"Discrete component vs. RFSoC solution cost comparison\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component-cost-compare.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/xilinx-discrete-component-cost-compare-300x101.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 3 \u2013 Discrete component vs. RFSoC solution cost comparison<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-b212a3d elementor-widget elementor-widget-spacer\" data-id=\"b212a3d\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f9f8a97 elementor-widget elementor-widget-text-editor\" data-id=\"f9f8a97\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">The cost of a typical multi-core ARM processor + (4 x Dual 5 GSPS A\/Ds) + (4 x Dual 10 GSPS D\/As)\n+ Kintex\u2122 UltraScale+ FPGA (with equivalent programmable logic and DSP density of the RFSoC) =\napproximately 2x the cost of the same functionality delivered in a single RFSoC.\n<\/p>\n\n<p class=\"p1\">While savings at any level is always welcome, the real benefit of the reduced cost can be seen in\nsystems where many channels of A\/Ds and D\/As are required. Massive multiple-input multipleoutput\n(MIMO) antennas are being targeted for applications from Wi-Fi to LTE to 5G. Massive MIMO\nantennas typically start at 8&#215;8 configurations (8 receive channels and 8 transmit channels) and can be\nmultiples of that configuration. This is a perfect match for the converters in the RFSoC.<\/p>\n<p class=\"p1\">\nAnother high channel count application is phased array radar. The Multi-function Phased Array\nRadar (MPAR) initiative combines the functions of several national radar networks into a single\nsystem for aircraft and weather surveillance. It is not uncommon for these antenna arrays to be\nspecified with 64 or more elements, with each element requiring an A\/D and D\/A pair combined\nwith signal generation and receive and control processing. With these systems as well as military\nsurveillance and targeting systems where hundreds of elements can be required, the savings found\nin RFSoC\u2019s integrated solution can add up quickly.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d2b82d0 elementor-widget elementor-widget-text-editor\" data-id=\"d2b82d0\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h2 style=\"color: #d10202; font-size: 23px;\">Data Converter Interfaces<\/h2>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-b059e5b elementor-widget elementor-widget-text-editor\" data-id=\"b059e5b\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">Up to this point the advantages of RFSoC have been primarily in improving on already available\nsolutions, saving on size, weight, power and cost compared to discrete component solutions. But by\nintegrating the data converters into the FPGA, RFSoC offers a solution that is currently unavailable\nusing existing technology. To understand this you must first look at how data converters connect to\nFPGAs. Using A\/Ds as an example (but this is the same for D\/As), connecting a 12-bit A\/D to an FPGA\nusing a parallel interface might look like this where each bit is represented by an LVDS pair and an\nadditional pair is used for data ready or clock.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-31d0f74 elementor-widget elementor-widget-image\" data-id=\"31d0f74\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"500\" height=\"335\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface.jpg\" class=\"attachment-large size-large wp-image-14435\" alt=\"A\/D converter to FPGA interface using parallel LVDS pairs\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface.jpg 500w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface-300x201.jpg 300w\" sizes=\"(max-width: 500px) 100vw, 500px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 4 \u2013 A\/D converter to FPGA interface using parallel LVDS pairs<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ee42738 elementor-widget elementor-widget-spacer\" data-id=\"ee42738\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-30b21a2 elementor-widget elementor-widget-text-editor\" data-id=\"30b21a2\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">In some cases the interface can make use of double data rate (DDR) technology where data is transferred\non the rising and falling edge of the clock, effectively doubling the amount of data transferred in a\nsingle clock cycle. But even with DDR, parallel converter interfaces become problematic for data\nconverters with sample rates above about 1.5 GHz due to the speed limitations of the LVDS interfaces\non FPGAs. One solution to overcome this is to use a 1:2 demultiplexed interface (DeMux) where data is sent over two parallel interfaces each running at half of the sample rate. In the 12-bit A\/D converter\nexample, if the converter is sampling at 2 GHz, each of the 12-bit paths following the DeMux are\nrunning at 1 GHz. This keeps each 12-bit interface below the maximum clock rate allowed by the\nFPGA LVDS interface but still delivers the data needed to support the 2 GHz sample rate.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ea911c4 elementor-widget elementor-widget-image\" data-id=\"ea911c4\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"214\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface-12.jpg\" class=\"attachment-large size-large wp-image-14436\" alt=\"\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface-12.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/AD-converter-FPGA-interface-12-300x107.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 5 \u2013 A\/D converter to FPGA interface using a 1:2 DeMux<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9ac392c elementor-widget elementor-widget-spacer\" data-id=\"9ac392c\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-058e5ac elementor-widget elementor-widget-text-editor\" data-id=\"058e5ac\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">But this solution also becomes problematic at higher speeds. Using this same technique, a 4 GHz A\/D\nwould require a 1:4 DeMux. This quickly starts to become a PCB design challenge when you consider\nthe number of pairs needed and that these signals need to be critically routed to maintain tight length\nmatching between pairs so data arrives at the FPGA across all 12 bits at the same time. In addition to\nthe routing challenge, a 12-bit A\/D converter now requires 4 sets of 12 pairs (or 96 individual I\/O pins,\nnot including clock pins) to interface to the FPGA. In a typical FPGA device where 400 to 600 I\/O pins\nmight be available for interfacing all parallel devices like A\/D and D\/A converters and memory, half the\npins could easily be used to connect just two 4 GHz A\/D converters.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-880701e elementor-widget elementor-widget-image\" data-id=\"880701e\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"239\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/parallel-vs-serial-PCB-routing.jpg\" class=\"attachment-large size-large wp-image-14437\" alt=\"Parallel vs. serial PCB routing\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/parallel-vs-serial-PCB-routing.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/parallel-vs-serial-PCB-routing-300x120.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 6 \u2013 Parallel vs. serial PCB routing<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d2dfe0b elementor-widget elementor-widget-spacer\" data-id=\"d2dfe0b\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a01b004 elementor-widget elementor-widget-text-editor\" data-id=\"a01b004\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">An alternate solution to the high-pin count interface is to use a serial interface to connect data\nconverters. JESD204 was created for this exact purpose. JESD204 makes use of the FPGA gigabit serial\ninterfaces instead of LVDS. The example below shows a PCB routed for a 1 GHz 12-bit A\/D connected\nvia parallel LVDS and a PCB routed for a similar 1 GHz 12-bit A\/D connected via four high speed serial\ninterfaces (or lanes) using JEDS204. The four lanes pose less of a PCB design challenge because of\nthe reduced number of signals as well as the fact that the interface standard includes clock and data\nrecovery features which eliminate the need to critically match the length of all lanes.<\/p>\n\n<p class=\"p1\">\nSo while JESD204 can be a good solution for many high speed data converter applications, it\u2019s not a\nperfect solution. The JESD204 IP and gigabit serial interface add about 1W to the power budget for\nevery four lanes used. JESD204 is a proprietary IP core and typically requires a paid license to use it.\nIn addition, using JESD204 can add complexity to the FPGA IP design. In applications where multiple\nconverters across multiple ICs need to be synchronized, JESD204 requires a more elaborate clocking\nsolution than parallel interfaces adding some additional circuitry and complexity. But while each of\nthese obstacles can add power, cost, complexity and increased size, none is typically a showstopper.<\/p>\n\n<p class=\"p1\">\nWhere JESD204 becomes a true impediment for some applications is in link latency. Where a parallel\nconverter interface can delay the data by at most a few sample clock cycles for local buffering, the JESD204\nprotocol and the SerDes required to support it can add 80 sample clock cycles or more of latency from\nwhen the data is converted to when it is available in the FPGA for an A\/D converter and in the reverse\ndirection for a D\/A converter. In some applications where data is streamed and processing results\nare not required in real-time, this poses no problem. As long as the data arrives at the FPGA\nwithout losing any samples, how long it takes to get there is not critical. But in many applications\nincluding high-speed tight control loop systems, some radar systems, and electronic warfare like countermeasures, where there is a very short time allowed for acquiring the data, processing it and\nturning it around, this latency is a non-starter and eliminates JESD204 based solutions.<\/p>\n\n<p class=\"p1\">\nSo, what does all this have to do with RFSoC? With the data converters integrated directly into the\nFPGA using parallel interfaces, they don\u2019t require the prohibitively high pin count external connections\nneeded for discrete parallel interface converters allowing more converter channels to be supported\nby a single FPGA. In addition, the latency associated with a JESD204 serial interface is not an issue.\nThis makes RFSoC an attractive to solution for high channel count and low latency applications.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-61f11e3 elementor-widget elementor-widget-text-editor\" data-id=\"61f11e3\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h2 style=\"color: #d10202; font-size: 23px;\">Hardware Design with RFSoC<\/h2>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d4ed648 elementor-widget elementor-widget-text-editor\" data-id=\"d4ed648\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">The circuit density and small size of the RFSoC create some unique challenges for circuit and PCB\ndesigners when engineering systems using the FPGA. Designing and laying out the PCB for the analog\ninterface containing 16 channels (8 A\/D and 8 D\/A), requires attention to even the smallest details, to\nmaintain signal quality and reduce crosstalk in such a dense configuration. Similarly, the RFSoCs GTYs\n(gigabit serial interfaces) are capable of running at higher than 32 Gb\/sec. This poses another layout\nand routing challenge to the PCB design to maintain these speeds with signal integrity. For some\noperating modes, the RFSoC requires up to nine different supply voltages. Add to that another four or\nfive supplies for peripheral circuitry and the power generation and management design can become\ncomplex very quickly. While each of these challenges can be demanding on their own, consider that\nmany of the applications where RFSoC can bring the greatest benefit are in space restricted and harsh\nenvironments, exacerbating the design challenge.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e856be9 elementor-widget elementor-widget-image\" data-id=\"e856be9\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"222\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/quartzXM-eXpress-module.jpg\" class=\"attachment-large size-large wp-image-14442\" alt=\"Mercury Systems QuartzXM eXpress Module\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/quartzXM-eXpress-module.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/quartzXM-eXpress-module-300x111.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 7 \u2013 Mercury Systems\u2019 QuartzXM eXpress Module<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a77df50 elementor-widget elementor-widget-spacer\" data-id=\"a77df50\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a0bbd92 elementor-widget elementor-widget-text-editor\" data-id=\"a0bbd92\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">Mercury Systems\u00ae has taken a unique approach to delivering\nRFSoC functionality to our customers. Our QuartzXM\u2122 eXpress\nModule is a small 2.5\u201d x 4\u201d board containing the Zynq UltraScale+\nRFSoC FPGA and all peripheral and power circuitry needed\nfor support and operation. The concept behind the QuartzXM\nis simple: to provide the RFSoC functionality in a small, fully\ndesigned package that can be used on different carriers as\nneeded to match the specific interface requirements of different\napplications. By offering the RFSoC on the QuartzXM, Mercury\nSystems is delivering not only the RFSoC functionality, but\nis delivering a solution where many of the most demanding\ncircuitry and packaging challenges have been solved.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-1f6337f elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"1f6337f\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-extended\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-b9912bc\" data-id=\"b9912bc\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-ccc4790 elementor-widget elementor-widget-image\" data-id=\"ccc4790\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/elementor\/thumbs\/quartz-3U-VPX-board-q27qbij2f3pg6s07oglfekaa09yg05tba510p36fuk.jpg\" title=\"quartz-3U-VPX-board\" alt=\"Mercury Systems\u2019 Model 5950 Quartz 3U VPX board\" loading=\"lazy\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 8 \u2013 Mercury Systems\u2019 Model 5950 Quartz 3U VPX board (cover removed to show QuartzXM Module)<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-920a326\" data-id=\"920a326\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-bffc7b1 elementor-widget elementor-widget-text-editor\" data-id=\"bffc7b1\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">Our Quartz\u2122 line includes board products in standard form\nfactors with 3U VPX, SOSA aligned 3U VPX, PCIe, SFF enclosure\nand SFF subsystems, delivering the QuartzXM in turn-key\nsolutions ready for immediate deployment. The products are\navailable in commercial and rugged, conduction cooled versions,\nand in many situations will be the final deployed solution. But\nwith the modular design of QuartzXM, the standard form factor\nboard can be the platform where the application is developed\nand proven, and then migrated to a custom carrier platform for\ndeployment.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-aee0842 elementor-widget elementor-widget-spacer\" data-id=\"aee0842\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-51982ca elementor-widget elementor-widget-text-editor\" data-id=\"51982ca\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h2 style=\"color: #d10202; font-size: 23px;\">Software and IP Design<\/h2>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a133722 elementor-widget elementor-widget-text-editor\" data-id=\"a133722\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">With each new family of FPGA, there has been a constant progression towards more powerful\nprocessing solutions. Each new family adds more logic density, faster logic fabric, more DSP resources,\nmore on-chip memory, faster interface and now with RFSoC high sample rate A\/D and D\/A converters.\nWhile these new capabilities are certainly welcome, and they do enable more and more complex\napplications to be targeted at FPGAs, they also raise the bar for better and more capable design tools\nto handle the increasing complexity and size of the new IP that can be created. Xilinx has addressed\nthe design tool challenge with their Vivado\u00ae Design Suite. It includes tools for every aspect of the\ndesign cycle. The latest version has improvements in performance with faster routing and more\nefficient FPGA resource usage allowing denser designs. Vivado also addresses the increasing design\ncomplexity challenges with tools for creating processing IP with C-language specification, an integrated\nsoftware development kit that targets the ARM processors, and plug-and-play block diagram based\nIP integration with IP Integrator. While all of these tool improvements go a long way in enabling both\nsoftware and IP engineers, the job of creating a complete system solution can be greatly accelerated\nwhen manufacturers of FPGA based hardware products provide IP and software libraries to support\nthe specific features of the hardware. The better the manufacturer can provide a foundation of\nsoftware and IP for the engineer to build their application on, the faster the engineer can complete\nthe job of producing a final, robust system.<\/p>\n\n<p class=\"p1\">All Mercury Systems hardware products include a full suite of FPGA based functions allowing the\nproduct to be used immediately in a range of applications without the need to create any FPGA IP. For\nSponsored by\nStrategies for Deploying Xilinx\u2019s Zynq UltraScale+ RFSoC 11\nall of our A\/D or D\/A based products the functions can include data acquisition and waveform generator\nengines, data tagging and metadata creation, VITA-49 packet creation, digital downconverters, multichannel\nand multi-board synchronization, optimized DMA for moving data on and off board through\nPCIe or 10GigE, in addition to IP targeted at specific applications.\n<\/p>\n\n<p class=\"p1\">RFSoC again brings new challenges and solutions with the sheer amount of data the A\/D and\nD\/A converters can introduce and the minimum latency interfaces between data converters and\nprogrammable logic in time critical applications. Mercury Systems\u2019 Quartz products address some\nof the most common requirements of RFSoC targeted applications with new built-in IP ready to use\nwith no additional IP design needed. These include an enhanced acquisition engine that supports the\nfull bandwidth 4 GHz sample rate with options to snapshot data to on-board memory or to stream\nover dual 100 GigE interfaces, an optimized x16 decimator for data reduction in high channel count\napplications, and an enhanced waveform generator engine for outputting D\/A data supplied by\nthe 100 GigE interface or from waveforms loaded to on-board memory. In each case the installed\nfunctions can provide a final solution or be the basis of a custom solution when built upon using the\nMercury Systems Navigator\u2122 FPGA Design Kit (FDK).<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-319a6a9 elementor-widget elementor-widget-image\" data-id=\"319a6a9\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"600\" height=\"304\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/mercury-navigator-FDK.jpg\" class=\"attachment-large size-large wp-image-14443\" alt=\"Mercury Systems\u2019s Navigator FDK\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/mercury-navigator-FDK.jpg 600w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/mercury-navigator-FDK-300x152.jpg 300w\" sizes=\"(max-width: 600px) 100vw, 600px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 9 \u2013 Mercury Systems\u2019s Navigator FDK allows FPGA engineers to access the board design in IP Integrator<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-410f06e elementor-widget elementor-widget-spacer\" data-id=\"410f06e\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d06be84 elementor-widget elementor-widget-text-editor\" data-id=\"d06be84\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">The Navigator FDK provides a library of all of Mercury Systems\u2019 IP functions as blocks that can be\nused in Xilinx\u2019s Vivado IP Integrator, giving the IP designer immediate access to the product\u2019s entire\nFPGA design as a block diagram. Individual IP blocks can be removed, modified, or replaced with\ncustom IP to meet the application\u2019s processing requirements. If at any time a designer needs to work\nwith the VHDL source code directly, it is always accessible in a source window, as well as full on-line\ndocumentation of every Mercury Systems IP core. Navigator FDK leverages the features of Vivado\nallowing an engineer to start designing with the FDK immediately without the need to learn new\nsoftware tools and streamlines the path to a final application solution by providing the foundation for\ncustom IP to be built on.<\/p>\n\n<p class=\"p1\">\nThe companion product to the Mercury Systems Navigator FDK is the Navigator Board Support Package\n(BSP). With every creation of, or modification to an IP block, a change to software, most likely running\non the RFSoC\u2019s ARM processors, to control the new or modified IP might be needed. The Navigator BSP\nwas designed to help manage this relationship between IP and software. The BSP provides C language\nfunctions and utilities structured to map the IP blocks provided in the FDK. This one-to-one relationship\nbetween IP and the software to control it is another path to manage the increasing complexity of\napplications.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-545477e elementor-widget elementor-widget-image\" data-id=\"545477e\" data-element_type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t<figure class=\"wp-caption\">\n\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"500\" height=\"275\" src=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/navigator.jpg\" class=\"attachment-large size-large wp-image-14444\" alt=\"Navigator\u2019s one-to-one relationship between BSP modules and IP modules\" srcset=\"https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/navigator.jpg 500w, https:\/\/www.vicmyers.com\/wp-content\/uploads\/2022\/04\/navigator-300x165.jpg 300w\" sizes=\"(max-width: 500px) 100vw, 500px\" \/>\t\t\t\t\t\t\t\t\t\t\t<figcaption class=\"widget-image-caption wp-caption-text\">Figure 10 \u2013 Navigator\u2019s one-to-one relationship between BSP modules and IP modules simplifies the task of keeping software changes synchronized with IP changes<\/figcaption>\n\t\t\t\t\t\t\t\t\t\t<\/figure>\n\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f0d4d08 elementor-widget elementor-widget-spacer\" data-id=\"f0d4d08\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-fd2db45 elementor-widget elementor-widget-text-editor\" data-id=\"fd2db45\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">RFSoC brings new possibilities for addressing some of the most challenging requirements of high\nbandwidth, high channel count systems. Understanding how this new technology can specifically address\nSWaP-C and low latency applications is key to matching it to many applications that can benefit from it\nthe most. And while Xilinx has provided a rich set of tools, IP and support at the chip level, equipment\nmanufactures like Mercury Systems, using RFSoC at the center of their board architecture, can leverage\nthe power of RFSoC by providing unique solutions to streamline the path from RFSoC to a deployed system.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9132525 elementor-widget elementor-widget-spacer\" data-id=\"9132525\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-07779fd elementor-widget elementor-widget-text-editor\" data-id=\"07779fd\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<h4>About Mercury Systems<\/h4>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e54d518 elementor-widget elementor-widget-text-editor\" data-id=\"e54d518\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<p class=\"p1\">Mercury is the leader in making trusted, secure mission-critical technologies profoundly more accessible to aerospace and defense.<\/p>\n<p class=\"p1\">Purpose.\nInnovation that Matters\u00ae\nBy and For People Who Matter<\/p>\n\n<p class=\"p1\">Vision.\nMake the world a safer, more secure place for all. Our goal is to provide all processing solutions on every system requiring uncompromised computing.<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-24f3d01 elementor-align-center elementor-widget elementor-widget-button\" data-id=\"24f3d01\" data-element_type=\"widget\" data-widget_type=\"button.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-button-wrapper\">\n\t\t\t<a class=\"elementor-button elementor-button-link elementor-size-sm\" href=\"https:\/\/www.vicmyers.com\/contact\/\">\n\t\t\t\t\t\t<span class=\"elementor-button-content-wrapper\">\n\t\t\t\t\t\t\t\t\t<span class=\"elementor-button-text\">Contact us<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-dfc1220 elementor-widget elementor-widget-spacer\" data-id=\"dfc1220\" data-element_type=\"widget\" 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elementor-share-btn_linkedin\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on linkedin\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fab-linkedin\" viewBox=\"0 0 448 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M416 32H31.9C14.3 32 0 46.5 0 64.3v383.4C0 465.5 14.3 480 31.9 480H416c17.6 0 32-14.5 32-32.3V64.3c0-17.8-14.4-32.3-32-32.3zM135.4 416H69V202.2h66.5V416zm-33.2-243c-21.3 0-38.5-17.3-38.5-38.5S80.9 96 102.2 96c21.2 0 38.5 17.3 38.5 38.5 0 21.3-17.2 38.5-38.5 38.5zm282.1 243h-66.4V312c0-24.8-.5-56.7-34.5-56.7-34.6 0-39.9 27-39.9 54.9V416h-66.4V202.2h63.7v29.2h.9c8.9-16.8 30.6-34.5 62.9-34.5 67.2 0 79.7 44.3 79.7 101.9V416z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_facebook\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on facebook\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fab-facebook\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M504 256C504 119 393 8 256 8S8 119 8 256c0 123.78 90.69 226.38 209.25 245V327.69h-63V256h63v-54.64c0-62.15 37-96.48 93.67-96.48 27.14 0 55.52 4.84 55.52 4.84v61h-31.28c-30.8 0-40.41 19.12-40.41 38.73V256h68.78l-11 71.69h-57.78V501C413.31 482.38 504 379.78 504 256z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_email\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on email\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fas-envelope\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M502.3 190.8c3.9-3.1 9.7-.2 9.7 4.7V400c0 26.5-21.5 48-48 48H48c-26.5 0-48-21.5-48-48V195.6c0-5 5.7-7.8 9.7-4.7 22.4 17.4 52.1 39.5 154.1 113.6 21.1 15.4 56.7 47.8 92.2 47.6 35.7.3 72-32.8 92.3-47.6 102-74.1 131.6-96.3 154-113.7zM256 320c23.2.4 56.6-29.2 73.4-41.4 132.7-96.3 142.8-104.7 173.4-128.7 5.8-4.5 9.2-11.5 9.2-18.9v-19c0-26.5-21.5-48-48-48H48C21.5 64 0 85.5 0 112v19c0 7.4 3.4 14.3 9.2 18.9 30.6 23.9 40.7 32.4 173.4 128.7 16.8 12.2 50.2 41.8 73.4 41.4z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\t<div class=\"elementor-grid-item\">\n\t\t\t\t\t\t<div\n\t\t\t\t\t\t\tclass=\"elementor-share-btn elementor-share-btn_print\"\n\t\t\t\t\t\t\trole=\"button\"\n\t\t\t\t\t\t\ttabindex=\"0\"\n\t\t\t\t\t\t\taria-label=\"Share on print\"\n\t\t\t\t\t\t>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-share-btn__icon\">\n\t\t\t\t\t\t\t\t<svg class=\"e-font-icon-svg e-fas-print\" viewBox=\"0 0 512 512\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\"><path d=\"M448 192V77.25c0-8.49-3.37-16.62-9.37-22.63L393.37 9.37c-6-6-14.14-9.37-22.63-9.37H96C78.33 0 64 14.33 64 32v160c-35.35 0-64 28.65-64 64v112c0 8.84 7.16 16 16 16h48v96c0 17.67 14.33 32 32 32h320c17.67 0 32-14.33 32-32v-96h48c8.84 0 16-7.16 16-16V256c0-35.35-28.65-64-64-64zm-64 256H128v-96h256v96zm0-224H128V64h192v48c0 8.84 7.16 16 16 16h48v96zm48 72c-13.25 0-24-10.75-24-24 0-13.26 10.75-24 24-24s24 10.74 24 24c0 13.25-10.75 24-24 24z\"><\/path><\/svg>\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-484a7a2 elementor-widget elementor-widget-spacer\" data-id=\"484a7a2\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-4c66870\" data-id=\"4c66870\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-d89009b elementor-search-form--skin-classic elementor-search-form--button-type-icon elementor-search-form--icon-search elementor-widget elementor-widget-global elementor-global-8245 elementor-widget-search-form\" data-id=\"d89009b\" data-element_type=\"widget\" data-settings=\"{&quot;skin&quot;:&quot;classic&quot;}\" data-widget_type=\"search-form.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<link rel=\"stylesheet\" href=\"https:\/\/www.vicmyers.com\/wp-content\/plugins\/elementor-pro\/assets\/css\/widget-theme-elements.min.css\">\t\t<search role=\"search\">\n\t\t\t<form class=\"elementor-search-form\" action=\"https:\/\/www.vicmyers.com\" method=\"get\">\n\t\t\t\t\t\t\t\t\t\t\t\t<div class=\"elementor-search-form__container\">\n\t\t\t\t\t<label class=\"elementor-screen-only\" for=\"elementor-search-form-d89009b\">Search<\/label>\n\n\t\t\t\t\t\n\t\t\t\t\t<input id=\"elementor-search-form-d89009b\" placeholder=\"Search...\" class=\"elementor-search-form__input\" type=\"search\" name=\"s\" value=\"\">\n\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\t<button 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elementor-widget-spacer\" data-id=\"433567a\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-7e2cafc elementor-widget elementor-widget-global elementor-global-8242 elementor-widget-heading\" data-id=\"7e2cafc\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h4 class=\"elementor-heading-title elementor-size-default\">We're Here to Help<\/h4>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e7c051b elementor-icon-list--layout-inline elementor-align-left open_chatbox elementor-list-item-link-full_width elementor-widget elementor-widget-global elementor-global-1937 elementor-widget-icon-list\" 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20.1 0 105.9-107.7 192-240 192-10.8 0-21.3-.8-31.7-1.9C207.8 439.6 281.8 480 368 480c41 0 79.1-9.2 111.3-25 21.8 12.7 52.1 25 88.7 25 3.2 0 6.1-1.9 7.3-4.8 1.3-2.9.7-6.3-1.5-8.7-.3-.3-22.4-24.2-35.8-54.5z\"><\/path><\/svg>\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-icon-list-text\">Live Chat >><\/span>\n\t\t\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-55e35f9 elementor-icon-list--layout-traditional elementor-list-item-link-full_width elementor-widget elementor-widget-global elementor-global-2012 elementor-widget-icon-list\" data-id=\"55e35f9\" data-element_type=\"widget\" data-widget_type=\"icon-list.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<ul class=\"elementor-icon-list-items\">\n\t\t\t\t\t\t\t<li class=\"elementor-icon-list-item\">\n\t\t\t\t\t\t\t\t\t\t\t<a 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class=\"elementor-icon-list-text\">info@vicmyers.com<\/span>\n\t\t\t\t\t\t\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t\t<\/li>\n\t\t\t\t\t\t<\/ul>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-c5475ce elementor-widget elementor-widget-global elementor-global-9807 elementor-widget-spacer\" data-id=\"c5475ce\" data-element_type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-17bb830 elementor-widget elementor-widget-global elementor-global-9166 elementor-widget-heading\" data-id=\"17bb830\" data-element_type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<h3 class=\"elementor-heading-title elementor-size-default\">Resources<\/h3>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-29eee3f elementor-grid-1 elementor-posts--thumbnail-none elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-widget elementor-widget-posts\" data-id=\"29eee3f\" data-element_type=\"widget\" data-settings=\"{&quot;classic_columns&quot;:&quot;1&quot;,&quot;classic_row_gap&quot;:{&quot;unit&quot;:&quot;px&quot;,&quot;size&quot;:20,&quot;sizes&quot;:[]},&quot;classic_columns_tablet&quot;:&quot;2&quot;,&quot;classic_columns_mobile&quot;:&quot;1&quot;,&quot;classic_row_gap_tablet&quot;:{&quot;unit&quot;:&quot;px&quot;,&quot;size&quot;:&quot;&quot;,&quot;sizes&quot;:[]},&quot;classic_row_gap_mobile&quot;:{&quot;unit&quot;:&quot;px&quot;,&quot;size&quot;:&quot;&quot;,&quot;sizes&quot;:[]}}\" data-widget_type=\"posts.classic\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<link rel=\"stylesheet\" href=\"https:\/\/www.vicmyers.com\/wp-content\/plugins\/elementor-pro\/assets\/css\/widget-posts.min.css\">\t\t<div class=\"elementor-posts-container elementor-posts elementor-posts--skin-classic elementor-grid\">\n\t\t\t\t<article class=\"elementor-post elementor-grid-item post-21436 post type-post status-publish format-standard has-post-thumbnail hentry category-product-news category-resources tag-daq tag-daq-system tag-data-acquisition tag-data-acquisition-recorder tag-data-acquisition-system\">\n\t\t\t\t<div class=\"elementor-post__text\">\n\t\t\t\t<h3 class=\"elementor-post__title\">\n\t\t\t<a href=\"https:\/\/www.vicmyers.com\/das1800-high-speed-data-acquisition-recorder\/\" >\n\t\t\t\tMeet the DAS1800 High Speed Data Acquisition Recorder\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<article class=\"elementor-post elementor-grid-item post-21286 post type-post status-publish format-standard has-post-thumbnail hentry category-product-news category-resources tag-embedded-atomic-clocks tag-global-navigation-satellite-system tag-network-timing tag-precision-time-protocol tag-timing-methods tag-timing-system\">\n\t\t\t\t<div class=\"elementor-post__text\">\n\t\t\t\t<h3 class=\"elementor-post__title\">\n\t\t\t<a href=\"https:\/\/www.vicmyers.com\/precise-time-scale-system-microchip-2\/\" >\n\t\t\t\tSecure Your Legacy Timing Systems From GNSS Threats\t\t\t<\/a>\n\t\t<\/h3>\n\t\t\t\t<\/div>\n\t\t\t\t<\/article>\n\t\t\t\t<article class=\"elementor-post elementor-grid-item post-20937 post type-post status-publish format-standard has-post-thumbnail hentry category-resources category-white-paper tag-data-acquisition tag-data-acquisition-recorder tag-data-acquisition-system tag-digital-storage-oscilloscopes tag-dso\">\n\t\t\t\t<div class=\"elementor-post__text\">\n\t\t\t\t<h3 class=\"elementor-post__title\">\n\t\t\t<a href=\"https:\/\/www.vicmyers.com\/all-in-one-data-acquisition-recorder\/\" >\n\t\t\t\tWhy Choose an All-in-One Data Acquisition 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IC.<\/p>\n","protected":false},"author":11,"featured_media":1103,"comment_status":"closed","ping_status":"open","sticky":false,"template":"elementor_header_footer","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"page-builder","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"disabled","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"disabled","ast-breadcrumbs-content":"","ast-featured-img":"disabled","footer-sml-layout":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center 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